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STLC5046
PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER
PRODUCT PREVIEW
PROGRAMMABLE MONOLITHIC 4 CHANNEL CODEC/FILTER SINGLE +3.3V SUPPLY PIN STRAP / MCU CONTROL MODE A/ LAW PROGRAMMABLE LINEAR CODING (16 BITS) OPTION PCM HIGHWAY FORMAT AUTOMATICALLY DETECTED: 1.536 or 1.544MHz; 2.048, 4.096, 8192 MHz TX GAIN PROGRAMMING: 16dB RANGE; <0.1dB STEP RX GAIN PROGRAMMING: 26dB RANGE; <0.1dB STEP PROGRAMMABLE TIME SLOT ASSIGNMENT DIGITAL AND ANALOG LOOPBACKS SLIC CONTROL PORT STATIC MODE (16 I/Os) DYNAMIC MODE (12 I/Os + 4 CS) 64 TQFP PACKAGE PCM IN HI-Z MODE DESCRIPTION The STLC5046 is a monolithic programmable 4 channel codec and filter. It operates with a single +3.3V supply. The analog interface is based on a receive output buffer driving the SLIC RX input and on an amplifier input stage. Due to the single supply voltage a proper midsupply reference level is generated internally by the device and all analog signals are referred to this level (AGND). The
TQFP64 ORDERING NUMBER: STLC5046
PCM interface uses one common 8KHz frame sync. pulse for transmit and receive direction. The bit clock can be selected between four standards: 1.536/1.544MHz, 2.048MHz, 4.096MHz, 8192MHz. Device programmability is achieved by means of 41 registers allowing to set the different parameters like TX/RX gains, encoding law (A/), time slot assignment, independent channels power up/down, loopbacks, PCM bits offset. Thanks to pinstrap option, the most significant of the above parameters can be set by hardware connection of dedicated pins. This allow to use this device also on line card without MCU on board. When pin strap option is selected different pins of the device will change their function (see pin description). In MCU control mode the STLC5046 can be programmed via serial interface running up to 4MHz. One interrupt output pin is also provided.
December 1999
This is preliminary information on a new product now in development. Details are subject to change without notice.
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STLC5046
BLOCK DIAGRAM
VCC VEE VDD VSS SUB CAP M1 M0
ANALOG FRONTEND
VFRO0
GR0 GR0
DIGITAL PROCESSOR
D/A sigma-delta 8bit A/u Law ENCODER 8bit
INTERPOLATORS
Post Filter
PCM INTERFACE & SLOT ASSGN
FS/FS0 MCLK TSX DX DR IO11 IO10 IO9 IO8 IO7 IO6 / FS3 IO5 / FS2 IO4 / FS1 IO3 / PD3 IO2 / GR3 IO1 / PD2 IO0 / GR2 CS3 / GX3 CS2 / GX2 CS1 / GX1 CS0 / GX0 INT / AMU CCLK / GR1 CI / PD0 CO / GR0 CS / PD1
VFRO1
GR1 GR0
Post Filter Post Filter RX FILTERS Post Filter PLL 17-bit Bus data
8-bit Bus
VFRO2
GR2 GR0
A/u Law DECODER
SLIC Programmable functions CONTROL PORT
VFRO3
GR3 GR0
PROGRAMMABLE GAIN RX
VFXI0
GX0
Anti-Alias
A/D
Anti-Alias
to analog FE
VFXI1
GX1
A/D
Anti-Alias
TX FILTERS
PROGRAMMABLE GAIN TX
VFXI2
GX2
A/D
Anti-Alias
contlol
CONFIG. REGISTERS
DECIMATORS
ARBITER
VFXI3
GX3
A/D
SERIAL CONTROL INTERFACE
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VDD VDI IOUT TSTG TLEAD VAI VCC to VEE VDD to VSS Digital Input Input Pin Voltage Output Pin Current Storage Temperature Range Lead Temperature (soldering, 10s) Analog Pin Input Voltage Parameter Value -0.5 to 4.6 -0.5 to 4.6 -0.5 to 5.5 1 -65 to +150 300 -0.5 to 4.6 Unit V V V mA C C V
OPERATING RANGE
Symbol VCC, VDD TOP Supply Voltage Operating Temperature Range Parameter Value 3.3 5% -40 to +85 Unit V C
THERMAL DATA
Symbol Rth j-amb Parameter Thermal Resistance Junction-Ambient Value 70 Unit C/W
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STLC5046
PIN CONNECTION (Top view)
CS2/GX2 CS3/GX3 IO6/FS3 VCC4 VEE4 VEE2 VEE3 IO10 IO11 RES N.C. N.C.
IO7
IO8
IO9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RES RES INT/AMU CS/PD1 CO/GR0 CI/PD0 CCLK/GR1 VSS VDD DR DX TSX MCLK FS/FS0 N.C. N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 N.C. N.C. CS0/GX0 CS1/GX1 VEE5 VEE1 IO4/FS1 IO0/GR2 IO1/PD2 IO2/GR3 IO3/PD3 IO5/FS2 VCC5 VEE0 N.C. M0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VFRO3 N.C. VFXI3 VCC3 VCC2 VFXI2 VFRO2 SUB CAP VFRO1 VFXI1 VCC1 VCC0 VFXI0 N.C. VFRO0
M1
D98TL405
PIN DESCRIPTION I/O DEFINITION
Type AI AO ODO DI DO DIO DTO DPS APS Analog Input Analog Output Open Drain Output Digital Input Digital Output Digital Input/Output Digital Tristate Output Digital Power Supply Analog Power Supply Definition
ANALOG
N. 33 39 42 48 Name VFRO0 VFRO1 VFRO2 VFRO3 Type AO AO AO AO Function Receive analog amplifier output channel 0. PCM data received on the programmed Time Slot on DR input is decoded and appears at this output. Receive analog amplifier output channel 1. PCM data received on the programmed Time Slot on DR input is decoded and appears at this output. Receive analog amplifier output channel 2. PCM data received on the programmed Time Slot on DR input is decoded and appears at this output. Receive analog amplifier output channel 3. PCM data received on the programmed Time Slot on DR input is decoded and appears at this output.
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STLC5046
PIN DESCRIPTION (continued) ANALOG
N. 35 38 43 46 40 Name VFXI0 VFXI1 VFXI2 VFXI3 CAP Type AI AI AI AI AI Function TX Input Amplifier channel 0. Typ 1M input impedance TX Input Amplifier channel 1. Typ 1M input impedance TX Input Amplifier channel 2. Typ 1M input impedance TX Input Amplifier channel 3. Typ 1M input impedance AGND Voltage filter pin. A 100nF capacitor must be connected between ground and this pin.
POWER SUPPLY
25, 36, VCC/0/1/2/3/ 37, 44, 4/5 45, 56, 26,30, VEE/0/1/2/3/ 4/5 31, 50, 51,55 9 8 41 VDD VSS SUB APS Total 6 pins: 3.3V analog power supplies, should be shorted together, require 100nF decoupling capacitor to VEE. Total 6 pins: analog ground, should be shorted together.
APS
DPS DPS DPS
Digital Power supply 3.3V, require 100nF decoupling capacitor to VSS. Digital Ground Substrate connection. Must be shorted together with VEE and VSS pins as close as possible the chip.
NOT CONNECTED
15, 16, 17, 18, 32, 34, 47, 49, 64 1,2,63 N.C. Not Connected.
RES
Reserved: must be left not connected.
DIGITAL
27 54 M0 M1 DI DI Mode select, see M1 M1 0 1 0 1 M0 1 0 0 1 Mode Select Pin-strap mode: Basic functions selected by proper pin strapping MCU mode: Device controlled via serial interface Reset status Not Allowed
13
MCLK
DI
Master Clock Input. Four possible frequencies can be used: 1.536/1.544 MHz; 2.048 MHz; 4.096 MHz; 8.192 MHz. The device automatically detect the frequency applied. This signal is also used as bit clock and it is used to shift data into and out of the DR and DX pins. Transmit Time Slot (open drain output, 3.2mA). Normally it is floating in high impedance state except when a time slot is active on the DX output. In this case TSX output pulls low to enable the backplane line driver. Transmit PCM interface. It remains in high impedance state except during the assigned time slots during wich the PCM data byte is shifted out on the rising edge of MCLK. Receive PCM interface. It remains inactive except during the assigned receive time slots during which the PCM data byte is shifted in on the falling edge of MCLK. Slic control I/O pin #7. Can be programmed as input or output via DIR register. Depending on content of CONF register can be a static input/output or a dynamic input/output synchronized with the CSn output signals controlling the SLICs.
12
TSX
ODO
11
DX
DTO
10 61
DR IO7
DI DIO
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STLC5046
PIN DESCRIPTION (continued) DIGITAL
N. 60 59 58 57 Name IO8 IO9 IO10 IO11 Type DIO DIO DIO DIO Function Slic control I/O pin #8. (see IO7 description). Slic control I/O pin #9. (see IO7 description). Slic control I/O pin #10. (see IO7 description). Slic control I/O pin #11. (see IO7 description).
DIGITAL (DUAL MODE)
14 FS/FS0 DI MCU control mode: FS. Frame Sync. Pulse. A pulse or a squarewave waveform with an 8kHz repetition rate is applied to this pin to define the start of the receive and transmit frame. Effective start of the frame can be then shifted of up to 7 clock pulses indipendently in receive and transmit directions by proper programming of the PCMSH register. Pin-strap control mode: FS0. Frame Sync. pulse of channel #0. One MCLK cycle long , starts PCM data transfer in the Time Slot following its falling edge (Short Frame Delayed Timing). MCU control mode: IO0. Slic control I/O pin #0. Can be programmed as input or output via DIR register. Depending on content of CONF register can be a static input/output or a dynamic input/output synchronized with the CSn output signals controlling the SLICs. Pin-strap control mode: GR2. Receive gain programming channel 2: 1: Receive gain = = -0.8dB 0: Rec. gain = -4.3dB MCU control mode: IO1. Slic control I/O pin #1. (see IO0 description). Pin-strap control mode: PD2. Power Down command channel 2: 1: Channel 2 Codec is in power down. (equivalent to CONF reg bit2 = 1) 0: Channel 2 Codec is in power up. (equivalent to CONF reg. bit2 = 0) MCU control mode: IO2. Slic control I/O pin #2. (see IO0 description) Pin-strap control mode: GR3. Receive gain programming channel 3. (see GR2 description) MCU control mode: IO3. Slic control I/O pin #3. (see IO0 description). Pin-strap control mode: PD3. Power Down command channel 3. (see PD2 description) MCU control mode: IO4 Slic control I/O pin #4. (see IO0 description). Pin-strap control mode: FS1. Frame Sync. pulse of channel #1. One MCLK cycle long , starts PCM data transfer in the Time Slot following its falling edge (Short Frame Delayed Timing). MCU control mode: IO4. Slic control I/O pin #5. (see IO0 description). Pin-strap control mode: FS2. Frame Sync. pulse of channel #1. One MCLK cycle long , starts PCM data transfer in the Time Slot following its falling edge (Short Frame Delayed Timing). MCU control mode: IO4. Slic control I/O pin #6. (see IO0 description). Pin-strap control mode: FS3. Frame Sync. pulse of channel #1. One MCLK cycle long , starts PCM data transfer in the Time Slot following its falling edge (Short Frame Delayed Timing).
19
IO0/GR2
DIO/DI
20
IO1/PD2
DIO/DI
21
IO2/GR3
DIO/DI
22
IO3/PD3
DIO/DI
23
IO4/FS1
DIO/DI
24
IO5/FS2
DIO/DI
62
IO6/FS3
DIO/DI
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STLC5046
PIN DESCRIPTION (continued)
N. 28 Name CS0/GX0 Type DO/DI Function MCU control mode: CS0. Slic CS control #0. Depending on CONF reg. content can be a CS output for SLIC #0 or a static I/O. When configured as CS output it is automatically generated by the Codec with a repetition time of 31.25s. In this mode also the IO11..0 are synchronized and carry proper data in and out synchronous with CS. Pin-strap control mode: GX0. Transmit gain programming channel 0: 1: Transmit gain = 0dB 0: Transmit gain = - 3.5dB MCU control mode: CS1: Slic CS control #1, (see CS0 description). Pin-strap control mode: GX1. Transmit gain programming channel 1 (see GX0 description) MCU control mode: CS2. Slic CS control #2, (see CS0 description). Pin-strap control mode: GX2. Transmit gain programming channel 2 (see GX0 description) MCU control mode: CS3. Slic CS control #3, (see CS0 description). Pin-strap control mode: GX3. Transmit gain programming channel 3 (see GX0 description) MCU control mode: CS. Chip Select of Serial Control Bus. When this pin is low control information can be written to or read from the device via the CI and CO pins. Pin-strap control mode: PD1. Power Down command channel 1. (see PD2 description). MCU control mode: CCLK. Clock of Serial Control Bus. This clock shifts serial control ilnformation into or out of CI or CO when CS input is low depending on the current instruction. CCLK may be asyncronous with the other system clocks. Pin-strap control mode: GR1. Receive gain programming ch. 1, (see GR2 description). MCU control mode: CI. Control Data Input of Serial Control Bus. Control data is shifted in the device when CS is low and clocked by CCLK. Pin-strap control mode: PD0. Power Down command channel 0. (see PD2 description).
29
CS1/GX1
DO/DI
53
CS2/GX2
DO/DI
52
CS3/GX3
DO/DI
4
CS/PD1
DI/DI
7
CCLK/GR1
DI/DI
6
CI/PD0
DI/DI
5
CO/GR0
DTO/DI MCU control mode: CO. Control Data Output of Serial Control Bus. Control data is shifted out the device when CS is low and clocked by CCLK. During the first 8 CCLK pulses the CO pin is H. I., valid data are shifted out during the following 8 CCLK pulses. Pin-strap control mode: GR0. Receive gain programming ch. 0, (see GR2 description). ODO/DI MCU control mode: INT. Interrupt output (open drain), goes low when a data change has been detected in the I/O pins. One mask registers allow to mask any I/O pin. Interrupt is reset when the I/O register is read. Pin-strap control mode: AMU. A/ law selection: AMU=0: law AMU=1: A law, even bit inverted
3
INT/AMU
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STLC5046
FUNCTIONAL DESCRIPTION POWER ON INITIALIZATION When power is first applied it is recommended to reset the device by forcing the condition M1.0=00, in order to to clear all the internal registers. In MCU mode M0 is set steadily Low and the device is reset by applying a negative pulse to M1 (its operative level in MCU mode is High); same result can be obtained by writing an High level into the control bit RES of the CONF register. In Pin-strap mode M1 is set steadily Low and the device is reset by applying a negative pulse to M0 (its operative level in Pin-strap mode is High); at the end of the Reset phase (M0=High) the device is programmed according to the logical configuration of the control pins. During the Reset condition all the I/On and CS_n pins are set as inputs , DX is set in high impedance and all VFROn outputsare forced to AGND. POWER DOWN STATE Each of the four channel may be put into power down mode by setting the appropriate bit in the CONF register or strapping to VDD the proper pin. In this mode the eventual programmed DX channel is set in high impedance while the VFRO outputs are forced to AGND. In Pin strap mode the value forced on the input pin is internally updated every FS signal. TRANSMIT PATH The analog VFXI signal through an amplifier stage is applied to a PCM converter and the corFigure 1. Transmit path.
TXG: 0dB +3.52dB VFXI
responding digital signal is sent to DX output. In MCU mode, the amplifier gain can be programmed with two different values by means of TXG Reg. : 0dB or +3.52 dB. A programmable gain block after the A/D conversion allows to set transmit gain in 12dB range, with steps <0.1dB by writing proper code into GTXn register. Setting GTXn=00h , the transmitted signal is muted, i.e. an idle PCM signal is generated on DX. A/ coding Law is selected by bit5 (AMU) of CONF reg. Setting LIN=1 (bit6 of CONF reg.) the Linear coding Law is selected (16bits); in this case the signal sent on DX will take two adjacent PCM time slots. In Pin-strap mode, the amplifier gain is set to 0dB; only two values of Transmit gain can be selected according to the level of GXn control input (in Pin-strap): GXn=1 selects the gain corresponding to GTXn=FFh (0dB) GXn=0 selects the gain corresponding to GTXn=8Fh ( -3.5dB) Different gain value is obtained through proper voltage divider. A/ coding Law is selected according to AMU pin level: AMU=0 -Law selected. AMU=1 A-Law selected. VFXI input must be AC coupled to the signal source; the voltage swing allowed is 1.0Vpp
conv.
1M AGND for TXG=0dB; GX=0dB (FF) 0dBm0 -15dBm|600
DX
GX
8 bit linear 1/4 to 1
A/
Figure 2. Receive path.
RXG: 0dB -1.94d B -4.44d B -7.96d B -13. 98dB VFRO for RXG=0dB; GR=0dB (FF) 0dBm0 => -3dBm|600
DR
A/
GR
8 bit linear 1/4 to 1
conv.
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STLC5046
Figure 3. MCU mode: Time - Slot Assignment
FS Receive Time Slot Transmit Time Slot FS
TS0
D7..................D 0
D7............... ...D0 .
TS23/31/61/12 7
DXAn Reg.
DRAn Reg.
when the preamplifier gain is set 0dB or 0.66Vpp if the gain is set to 3.52dB (MCU mode only); higher levels must be reduced through proper dividers. Typical impedance of VFXI input is 1Mohm.
RECEIVE PATH The received PCM signal DR through the decoder section, the gain select block and the D/A converter is converted in an analog signal which is transfered to VFRO output through an amplifier stage. In MCU mode a programmable gain block before the A/D conversion allows to set receive gain in 12dB range, with steps <0.1dB by writing proper code into GRXn register. The amplifier gain can be programmed with five different values by means of RXG Register: 0dB -1.94dB -4.44dB -7.96dB -13.98dB. Setting GRXn=00h , the receive signal is muted and VFRO output is set to AGND. A/ coding Law is selected by bit5 (AMU) of CONF reg. Setting LIN = 1 (bit6 of CONF reg.) the Linear coding Law is selected (16bits); in this case the signal received on DR will take two adjacent PCM time slots. in pin Strap mode only two values of Receive Gain can be selected according to the level of GRn control input (in Pin Strap) GRn = 1 selects the gain corresponding to GRXn = E2h, RXG = 0dB (-0.8dB) GRn = 0 selects the gain corresponding to GRXn = AFh, RXG = -1.94dB (-4.3dB) Different gain value is obtained through proper voltage divider.
A/ coding Law is selected according to AMU pin level: AMU=0 -Law selected. AMU=1 A-Law selected. VFRO output, referred to AGND must be AC coupled to the load, referred to VSS, to prevent a DC current flow. VFRO has a drive capability of 1.0mA (peak value), with a max AC swing of 2Vpp. In order to get the best noise performances it is recommended to keep the GRX value as close as possible to the maximum (FFh) setting properly the additional attenuation by means of RXG. PCM INTERFACE The STLC5046 dedicate five pins (six in pin strap mode) to the interface with the PCM highways. MCLK represents the bit clock and is also used by the device as a source for the clock of the internal Sigma Delta converter timings. Four possible frequencies can be used: 1.536/1.544MHz (24 channels PCM frame); 2048MHz (32 channels PCM frame); 4.096MHz (64 channels PCM frame); 8.192MHz (128 channels PCM frame). The operating frequency is automatically detected by the device when both MCLK and FS are applied. MCLK is synchronizing both the transmit data (DX) and the receive data (DR). MCU mode: The Frame Sync. signal FS is the common time base for all the four channels; Short (one MCLK period) or Long (more than one MCLK period) FS are allowed. Transmit and Receive programmable Time-Slots are framed to an internal sync. signal that can be coincident with FS or delayed of 1 to 7 MCLK cycles depending on the programming of PCMSH
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STLC5046
Figure 4. Pin Strap mode: Time Slot Assignment
Receive /Transmit Time Slot CH0 CHn CHm
D7...................D0 FS0 FSn
D7..................D0
D7...................D0
TS23/31/61/127
FSm
register. DX represent the transmit PCM interface. It remains in high impedance state except during the assigned time slots during which the PCM data byte is shifted out on the rising edge of MCLK. The four channels can be shifted out in any possible timeslot as defined by the DXA0 to DXA3 registers. If one codec is set in Power Down by software programming the corresponding timeslot is set in High Impedance. When linear coding mode is selected by CONF register programming the output channel will need two consecutive timeslots (see register description). DR represent the receive PCM interface. It remains inactive except during the assigned time slots during wich the PCM data byte is shifted in on the falling edge of MCLK. The four channels are shifted in any possible timeslot as defined by the DRA0 to DRA3 registers. Pin Strap Mode When pinstrap mode is selected, dedicated Frame Sync. FS3..0 are provided on dual function pins:
MCU FS IO4 IO5 IO6 Pin-strap FS0 FS1 FS2 FS3 Pin 12 17 18 48
(Transmit and Receive) takes place in the 8 MCLK cycles following the falling edge of FSn in case of Short Frame or the rising edge in case of Long Frame. If one codec is set in Power Down by proper pin strap configuration the corresponding timeslot is not loaded and the VFRO output is kept at steady AGND level. Finally by means of the LOOPB register is possible to implement a digital or analog loopback on any of the selected channels. TSX represent the Transmit Time Slot (open drain output, 3.2mA). Normally it is floating in high impedance state except when a time slot is active on the DX output. In this case TSX output pulls low to enable the backplane line driver. Should be strapped to VSS when not used. Table 1. Control byte structure.
First Byte (Address) 7 R/W D7 6 D/S D6 5 A5 D5 4 A4 D4 3 A3 D3 2 A2 D2 1 A1 D1 0 A0 D0
R/W = 0: Write Register R/W = 1: Read Register D/S = 0: Single byte D/S = 1: Two bytes A5..A0: Register Address
The PCMSH register cannot be accessed, therefore the beginning of the transmit and receive frame is identified by the rising edge of the FSn signal. Each channel has its dedicated Frame Sync. signal FSn. Short or Long frame timing is automatically selected; depending on the FS signal applied to FS0 input. The assigned Time Slot
CONTROL INTERFACE STLC5046 has two control modes, a microprocessor control mode and a pin strap control mode. The two modes are selected by M0 and M1 pins. When M0 = low, M1 = high (MCU control mode) the MCU port is activated; and the 41 registers of the device can be programmed. When M0 = high, M1 = low (Pin-strap mode) the microprocessor control port is disabled and some of the digital pins change their function allowing to perform a very basic programming of the device.
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STLC5046
In pin-strap mode the status of the control pins is entered at power-on reset and refreshed at any Frame Sync. cycle. In MCU mode the control information is written to or read from STLC5046 via the serial four wires control bus : CCLK : Control Clock CS : Chip Select input CI : Serial Data input CO : Serial Data output All control instructions require 2 bytes, with the exception of the single byte for command synchronization. The first byte specify the register address, and the type of access (Read or Write). The second byte contain the data to be loaded into the register (on CI wire) or carried out the register content (on CO wire) depending on the R/W bit of the first byte. CO wire is normally in High Impedance and goes to low impedance only during the second byte in case of Read operation. This allows to use a common wire for both CI/CO. Serial data CI is shifted to the serial input register on the rising edge of CCLK and CO is shifted out on the falling. CS, normally High, is set Low during the transmission / reception of a byte, lasting 8CCLK pulses . Though, in general, two bytes of the same instruction take two CS separated cycles , STLC5046 can handle the data transfer in a single 16 CCLK CS cycle, in both the directions. One additional wire provided to the control interface is an open drain interrupt output (INT) that goes low when a change of status is detected on the I/O pins. SLIC CONTROL INTERFACE The device provides 12 I/O pins plus 4 CS signals. The interface can work in dynamic or static mode: it can be selected by means of DIR register. Dynamic Mode: the I/O pins are configured as input or output by means of DIR register. The CS signals are used to select the different SLIC interface. In this case the I/O pin can be multiplexed. The data loaded from SLIC#n via I/O pins configured as input can be read in the DATAn register. The data written in a DATAn register will be loaded on the I/O pins configured as output when the Csn signal will be active. Static Mode: The CS signal can be used as I/O pins. They can be configured as input or output I/O by means of DATA1 register. The data corresponding to the CS signal can be read or written by means of DATA2 register. All data related to th other I/O pins can be read or written by means of DATA0 register.
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REGISTERS ADDRESSES (only MCU mode)
Addr. 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 31h Name CONF DIR-L DIR-H DATA0-L DATA0-H DATA1-L DATA1-H DATA2-L DATA2-H DATA3-L DATA3-H GTX0 GTX1 GTX2 GTX3 GRX0 GRX1 GRX2 GRX3 DXA0 DXA1 DXA2 DXA3 DRA0 DRA1 DRA2 DRA3 PCMSH DMASK-L DMASK-H CMASK PCHK-A PCHK-B INT ALARM AMASK LOOPB TXG RXG-1,0 RXG-3,2 SRID Description Configuration Register I/O Direction (bit 7-0) I/O Direction (bit 11-8) I/O Data ch#0/ Static Data; (bit 7-0) I/O Data ch#0/ Static Data ; (bit 11-8) I/O Data ch#1 (bit 7-0) / CS Direction I/O Data ch#1 (bit 11-8) I/O Data ch#1 (bit 7-0) / CS Data I/O Data ch#2 (bit 11-8) I/O Data ch#3 (bit 7-0) I/O Data ch#3 (bit 11-8) Transmit Gain ch#0 Transmit Gain ch#1 Transmit Gain ch#2 Transmit Gain ch#3 Receive Gain ch#0 Receive Gain ch#1 Receive Gain ch#2 Receive Gain ch#3 Transmit Timeslot ch#0 Transmit Timeslot ch#1 Transmit Timeslot ch#2 Transmit Timeslot ch#3 Receive Timeslot ch#0 Receive Timeslot ch#1 Receive Timeslot ch#2 Receive Timeslot ch#3 PCM Shift Register Interrupt Mask I/O Port (03h) Interrupt Mask I/O Port (04h) Interrupt Mask I/O Port (07h) Persistency Check Time for Input A Persistency Check Time for Input B Interrupt Register Alarm Register Interrupt Mask for Alarm Loopback Register Transmit preamp. Gain Receive preamp. Gain (ch1 ch0) Receive preamp. Gain (ch3 ch2) Silicon revision identification code
STLC5046
REGISTERS DESCRIPTION Configuration Register (CONF) Addr=00h; Reset Value=3Fh
Bit7 RES Bit6 LIN Bit5 AMU Bit4 STA Bit3 PD3 Bit2 PD2 Bit1 PD1 Bit0 PD0
I/O Data Register channel #0 (DATA0) Addr=03h; Reset Value=00h Addr=04h; Reset Value=X0h If bit 4 of CONF register (STA)=0 Dynamic I/O mode:
Bit7 Bit6 D06 Bit5 D05 Bit4 D04 Bit3 D03 D011 Bit2 D02 D010 Bit1 D01 D09 Bit0 D00 D08
RES=0Normal Operation RES=1 Device Reset: I/0n and CSn are all inputs, DX is H.I. (equivalent to Hw. reset). LIN=0 A or law PCM encoding LIN=1 Linear encoding (16 bits), two's complement. AMU=0 law selection AMU=1 A law selection (even bits inverted) STA=0 CS0 to CS3 scan the four SLICs connected to the I/O control port, each CS has a 31.25s repetition time. STA=1; I/O are static, CS0 to CS3 are configured as generic static I/O PD3..0=0 Codec 3..0 is active PD3..0=1 Codec 3..0 is in power Down. When one codec is in Power Down the corresponding VFRO output is forced to AGND. and the corresponding transmit time slot on DX is set in H.I. Pin strap value:
RES 0 AMU 0 PD3 PD2 PD1 PD0
D07
When CS0 is active D011..0 are transferred to the corresponding I/O pins configured as outputs (see DIR register). For the I/O pins configured as inputs the corresponding D011..0 will be written by the values applied to those pins while CS0 is low. If bit 4 of CONF register (STA)=1 Static I/O mode:
Bit7 DS7 Bit6 DS6 Bit5 DS5 Bit4 DS4 Bit3 DS3 Bit2 DS2 Bit1 DS1 DS9 Bit0 DS0 DS8
DS11 DS10
D11..0 are transferred to the corresponding I/O pins configured as outputs (see DIR register). For the I/O pins configured as inputs the corresponding D11..0 will be written by the values applied to those pins. Pin strap value:
0 0 0 0 0 0 0 0 0 0 0 0
I/O Direction Register (DIR) Addr=01h; Reset Value=00h Addr=02h; Reset Value=X0h
Bit7 IO7 Bit6 IO6 Bit5 IO5 Bit4 IO4 Bit3 IO3 IO11 Bit2 IO2 IO10 Bit1 IO1 IO9 Bit0 IO0 IO8
I/O Data Register channel #1 (DATA1) Addr=05h; Reset Value=00h Addr=06h; Reset Value=X0h If bit 4 of CONF register (STA)=0 Dynamic I/O mode:
Bit7 D17 Bit6 D16 Bit5 D15 Bit4 D14 Bit3 D13 D111 Bit2 D12 D110 Bit1 D11 D19 Bit0 D10 D18
IO11..0 = 0; I/O pin 11..0 is an input, data on the I/O input is written in DATAn register bit 11..0. IO11..0 = 1; I/O pin 11..0 is an output, data contained in DATAn register bit11..0 is transferred to the I/O output. Pin strap value:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
When CS1 is active D11..0 are transferred to the corresponding I/O pins configured as outputs (see DIR register). For the I/O pins configured as inputs the corresponding D11..0 will be written by the values applied to those pins while CS1 is low. If bit 4 of CONF register (STA)=1
11/27
STLC5046
Static I/O mode:
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
CIO3 CIO2 CIO1 CIO0
I/O Data Register channel #3 (DATA3) Addr=09h; Reset Value=00h Addr=0Ah; Reset Value=X0h Used only if bit 4 of CONF register (STA)=0; Dynamic I/O mode:
Bit7 D37 Bit6 D36 Bit5 D35 Bit4 D34 Bit3 D33 Bit2 D32 Bit1 D31 D39 Bit0 D30 D38
CIO0..3=0 The CS0..3 is a static input, DATA is written in DATA2 register bits 0..3. CIO0..3=1 The CS0..3 is a static output, DATA is taken from DATA2 register bits 0..3. Pin strap value:
0 0 0 0 0 0 0 0 0 0 0 0
D311 D310
I/O Data Register channel #2 (DATA2) Addr=07h; Reset Value=00h Addr=08h; Reset Value=X0h If bit 4 of CONF register (STA)=0 Dynamic I/O mode:
Bit7 D27 Bit6 D26 Bit5 D25 Bit4 D24 Bit3 D23 D211 Bit2 D22 D210 Bit1 D21 D29 Bit0 D20 D28
When CS3 is active D11..0 are transferred to the corresponding I/O pins configured as outputs (see DIR register). For the I/O pins configured as inputs the corresponding D11..0 will be written by the values applied to those pins while CS3 is low. If bit4 of CONF register (STA)=1 Static I/O mode: can be used as general purpose R/W registers, without any direct action on the control of the device. Pin strap value:
0 0 0 0 0 0 0 0 0 0 0 0
Transmit Gain channel #0 (GTX0) Addr=0Bh; Reset Value=00h
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
When CS2 is active D211..0 are transferred to the corresponding I/O pins configured as outputs (see DIR register). For the I/O pins configured as inputs the corresponding D11..0 will be written by the values applied to those pins while CS2 is low. If bit 4 of CONF register (STA)=1 Static I/O mode:
Bit7 Bit6 Bit5 Bit4 Bit3 CD3 Bit2 CD2 Bit1 CD1 Bit0 CD0
00h:Stop any trasmit signal, null level is transmitted in the corresponding timeslot on DX output. >00h:Digital gain is inserted in the TX path equal to: 20log[0.25+0.75*(progr.value/256)] Pin strap values: GX0=1: 0dB gain (value = FFh):
1 1 1 1 1 1 1 1
CD3..0 are transferred to the corresponding CS pin if configured as static output (see register DATA1). For the CS pins configured as static inputs the corresponding CD3..0 will be written by the values applied to those pins. Pin strap value:
0 0 0 0 0 0 0 0 0 0 0 0
GX0=0: -3.5dB gain (value = 8Fh):
1 0 0 0 1 1 1 1
Transmit Gain channel #1 (GTX1) Addr=0Ch; Reset Value=00h
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
00h:Stop any trasmit signal, null level is transmit12/27
STLC5046
ted in the corresponding timeslot on DX output. >00h:Digitalgain is inserted in the TX path equalto: 20log[0.25+0.75*(progr.value/256)] Pin strap values: GX0=1: 0dB gain (value = FFh):
1 1 1 1 1 1 1 1
Receive Gain channel #0 (GRX0) Addr=0Fh; Reset Value=00h
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
GX0=0: -3.5dB gain (value = 8Fh):
1 0 0 0 1 1 1 1
00h:Stop any received signal, AGND level is forced on the VFRO0 analog output. >00h:Digitalgain is inserted in the RX path equalto: 20log[0.25+0.75*(progr.value/256)] Pin strap values: GR0=1: -0.8dB gain (value = E2h):
1 1 1 0 0 0 1 0
Transmit Gain channel #2 (GTX2) Addr=0Dh; Reset Value=00h
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
GR0=0: -2.36dB gain (value = AFh):
1 0 1 0 1 1 1 1
00h: Stop any trasmit signal, null level is transmitted in the corresponding timeslot on DX output. >00h:Digitalgain is inserted in the TX path equalto: 20log[0.25+0.75*(progr.value/256)] Pin strap values: GX0=1: 0dB gain (value = FFh):
1 1 1 1 1 1 1 1
Overall gain including also RXG: GR0 = 1:-0.8dB; GR0 = 0: -4.3dB Receive Gain channel #1 (GRX1) Addr=10h; Reset Value=00h
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
GX0=0: -3.5dB gain (value = 8Fh):
1 0 0 0 1 1 1 1
Transmit Gain channel #3 (GTX3) Addr=0Eh; Reset Value=00h
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
00h:Stop any received signal, AGND level is forced on the VFRO1 analog output. >00h:Digitalgain is inserted in the RX path equalto: 20log[0.25+0.75*(progr.value/256)] Pin strap values: GR1=1: -0.8dB gain (value = E2h):
1 1 1 0 0 0 1 0
GR1=0: -2.36dB gain (value = AFh): 00h:Stop any trasmit signal, null level is transmitted in the corresponding timeslot on DX output. >00h:Digitalgain is inserted in the TX path equalto: 20log[0.25+0.75*(progr.value/256)] Pin strap values: GX0=1: 0dB gan (value = FFh):
1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1
Overall gain including also RXG: GR1= 1:-0.8dB; GR1 = 0: -4.3dB Receive Gain channel #2 (GRX2) Addr=11h; Reset Value=00h
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
GX0=0: -3.5dB gain (value = 8Fh):
1 0 0 0 1 1 1 1
00h:Stop any received signal, AGND level is forced on the VFRO2 analog output. >00h:Digitalgain is inserted in the RX path equalto:
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STLC5046
20log[0.25+0.75*(progr.value/256)] Pin strap values: GR2=1: -0.8dB gain (value = E2h):
1 1 1 0 0 0 1 0
Example: if T06..T00=00:
TS0 15 14 13 12 11 10 9 8 7 6 5 TS1 43 21 0
Pin strap value (value 80h):
1 0 0 0 0 0 0 0
GR2=0: -2.36dB gain (value = AFh):
1 0 1 0 1 1 1 1
Referred to FS0. Transmit Time Slot channel#1 (DXA1) Addr=14h; Reset Value=00h
Bit7 EN1 Bit6 T16 Bit5 T15 Bit4 T14 Bit3 T13 Bit2 T12 Bit1 T11 Bit0 T10
Overall gain including also RXG: GR2 = 1:-0.8dB; GR2 = 0: -4.3dB Receive Gain channel #3 (GRX3) Addr=12h; Reset Value=00h
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
EN1=0:
00h:Stop any received signal, AGND level is forced on the VFRO3 analog output. >00h:Digitalgain is inserted in the TX path equalto: 20log[0.25+0.75*(progr.value/256)] Pin strap values: GR3=1: -0.8dB gain (value = E2h):
1 1 1 0 0 0 1 0
GX3=0: -4.3dB gain (value = AFh):
1 0 1 0 1 1 1 1
Selected transmit time slot on DX output is in H.I. EN1=1: Selected transmit time slot on DX output is active carrying out the PCM encoded signal of VFXI1. T16..0:Define time slot number (0 to 127) on which PCM encoded signal of VFXI1 is carried out. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows: the 8 most significative bits in the programmed time slot, the 8 least significative bits in the following timeslot. Example: if T16..T10=00:
TS0 15 14 13 12 11 10 9 8 7 6 5 TS1 43 21 0
Overall gain including also RXG: GR3 = 1:-0.8dB; GR3 = 0: -4.3dB Transmit Time Slot channel #0 (DXA0) Addr=13h; Reset Value=00h
Bit7 EN0 Bit6 T06 Bit5 T05 Bit4 T04 Bit3 T03 Bit2 T02 Bit1 T01 Bit0 T00
Pin strap value (value=80h)
1 0 0 0 0 0 0 0
Referred to FS1. Transmit Time Slot channel #2 (DXA2) Addr=15h; Reset Value=00h
Bit7 EN2 Bit6 T26 Bit5 T25 Bit4 T24 Bit3 T23 Bit2 T22 Bit1 T21 Bit0 T20
Selected transmit time slot on DX output is in H.I. EN0=1: Selected transmit time slot on DX output is active carrying out the PCM encoded signal of VFXI0. T06..0: Define time slot number (0 to 127) on which PCM encoded signal of VFXI0 is carried out. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows: the 8 most significative bits in the programmed time slot, the 8 least significative bits in the following timeslot.
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EN0=0:
EN2=0:
Selected transmit time slot on DX output is in H.I. EN2=1: Selected transmit time slot on DX output is active carrying out the PCM encoded signal of VFXI2. T26..0:Define time slot number (0 to 127) on which PCM encoded signal of VFXI2 is carried out. If linear mode is selected (LIN=1 of CONF regis-
STLC5046
ter) the 16 bits will be carried out as follows: the 8 most significative bits in the programmed time slot, the 8 least significative bits in the following timeslot. Example: if T26..T20=00:
TS0 15 14 13 12 11 10 9 87 65 TS1 4 32 10
on carrying the PCM signal to be decoded and tranferred to VFRO0 output.If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as follows: the 8most significative bits in the programmed time slot, the 8 least significative bits in the following timeslot. Example: if R06..R00=00:
TS0 15 14 13 12 11 10 9 8 7 6 5 TS1 43 21 0
Pin strap value (value=80h)
1 0 0 0 0 0 0 0
Pin strap value (value 80h):
1 0 0 0 0 0 0 0
Referred to FS2. Transmit Time Slot channel #3 (DXA3) Addr=16h; Reset Value=00h
Bit7 EN3 Bit6 T36 Bit5 T35 Bit4 T34 Bit3 T33 Bit2 T32 Bit1 T31 Bit0 T30
Referred to FS0. Receive Time Slot channel #1 (DRA1) Addr=18h; Reset Value=00h
Bit7 EN0 Bit6 R16 Bit5 R15 Bit4 R14 Bit3 R13 Bit2 R12 Bit1 R11 Bit0 R10
EN3=0:
Selected transmit time slot on DX output is in H.I. EN3=1: Selected transmit time slot on DX output is active carrying out the PCM encoded signal of VFXI3. T36..0:Define time slot number (0 to 127) on which PCM encoded signal of VFXI3 is carried out. If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows: the 8 most significative bits in the programmed time slot, the 8 least significative bits in the following timeslot. Example: if T36..T30=00:
TS0 15 14 13 12 11 10 9 87 65 TS1 4 32 10
Disable reception of selected time slot. Selected receive time slot on DR input is PCM decoded and tranferred to VFRO1 output. R16..0:Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded and tranferred to VFRO1 output.If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as follows: the 8most significative bits in the programmed time slot, the 8 least significative bits in the following timeslot. Example: if R16..R10=00:
TS0 15 14 13 12 11 10 9 8 7 6 5 TS1 43 21 0
EN1=0: EN1=1:
Pin strap value (value=80h)
1 0 0 0 0 0 0 0
Pin strap value (value=80h)
1 0 0 0 0 0 0 0
Referred to FS3. Receive Time Slot channel #0 (DRA0) Addr=17h; Reset Value=00h
Bit7 EN0 Bit6 R06 Bit5 R05 Bit4 R04 Bit3 R03 Bit2 R02 Bit1 R01 Bit0 R00
Referred to FS1. Receive Time Slot channel #2 (DRA2) Addr=19h; Reset Value=00h
Bit7 EN2 Bit6 R26 Bit5 R25 Bit4 R24 Bit3 R23 Bit2 R22 Bit1 R21 Bit0 R20
Disable reception of selected time slot. Selected receive time slot on DR input is PCM decoded and tranferred to VFRO0 output. R06..0:Define receive time slot number (0 to 127)
EN0=0: EN0=1:
EN2=0: EN2=1:
Disable reception of selected time slot. Selected receive time slot on DR input is PCM decoded and tranferred to VFRO1 output. R26..0:Define receive time slot number (0 to 127)
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STLC5046
on carrying the PCM signal to be decoded and tranferred to VFRO2 output.If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as follows: the 8most significative bits in the programmed time slot, the 8 least significative bits in the following timeslot. Example: if R26..R20=00:
TS0 15 14 13 12 11 10 9 87 65 TS1 4 32 10
FS rising edge. Pin strap value (value=00h):
0 0 0 0 0 0 0 0
Interrupt Mask Register for I/O port (DMASK) Addr=1Ch; Reset Value=FFh Addr=1Dh; Reset Value=XFh
Bit7 MD7 Bit6 MD6 Bit5 MD5 Bit4 MD4 Bit3 MD3 Bit2 MD2 Bit1 Bit0
Pin strap value (value=80h)
1 0 0 0 0 0 0 0
MD1 MD0
MD11 MD10 MD9 MD8
Referred to FS2. Receive Time Slot channel #3 (DRA3) Addr=1Ah; Reset Value=00h
Bit7 EN3 Bit6 R36 Bit5 R35 Bit4 R34 Bit3 R33 Bit2 R32 Bit1 R31 Bit0 R30
EN3=0: EN3=1:
Disable reception of selected time slot. Selected receive time slot on DR input is PCM decoded and tranferred to VFRO1 output. R36..0:Define receive time slot number (0 to 127) on carrying the PCM signal to be decoded and tranferred to VFRO2 output.If linear mode is selected (LIN=1 of CONF register) the 16 bits will be used as linear code as follows: the 8most significative bits in the programmed time slot, the 8 least significative bits in the following timeslot. Example: if R36..R30=00:
TS0 15 14 13 12 11 10 9 87 65 TS1 4 32 10
MD11..0=1: The corresponding I/O doesn't generate interrupt. MD11..0=0: The corresponding I/O (programmed as Input) generate interrupt if a change of status is detected. Input lines with persistency check generate interrupt if the changed status remains stable longer than the time programmed in the persistency check registers PCHKA/B. Lines without persistance check generate an immediate interrupt request. Mask register has no effect on those pins configured as outputs, those pins will not generate interrupt. Pin strap value.
1 1 1 1 1 1 1 1 1 1 1 1
Interrupt Mask Register for CD port (CMASK) Addr=1Eh; Reset Value=XFh
Bit7 Bit6 Bit5 Bit4 Bit3 MC3 Bit2 MC2 Bit1 Bit0
Pin strap value (value=80h)
1 0 0 0 0 0 0 0
MC1 MC0
Referred to FS3. PCM Shift Register (PCMSH) Addr=1Bh; Reset Value=00h
Bit7 Bit6 XS2 Bit5 XS1 Bit4 XS0 Bit3 Bit2 RS2 Bit1 RS1 Bit0 RS0
XS2..0:Effective start of the TX frame is the programmed values of clock pulses (0 to 7) after the FS rising edge. RS2..0:Effective start of the RX frame is the programmed values of clock pulses (0 to 7) after the
16/27
In MCU mode, dynamic I/O configuration, MCn bits are the disable/enable interrupt related to the channel n : MC3..0= 0 Any I/O line of the related channel is enabled to generate interrupt depending on DMASK setting. MC3..0=1 Any I/O line of the related chanel is disabled to generate interrupt indipendently of DMASK setting. In MCU mode, static I/O configuration, MCn bits are the interrupt mask bits related to CSn that are configured as I/O lines. MC3..0=1: The corresponding I/O doesn't generate interrupt. MC3..0=0: The corresponding I/O generate interrupt if a change of status is detected.
STLC5046
Input lines with persistency check generate interrupt if the changed status remains stable longer than the time programmend in the persistency check registers PCHKA/B Lines without persistency check generate an immediate interrupt request. Mask register has no effect on those pins configured as outputs, those pins will not generate interrupt. Pin strap value (value=00h):
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Interrupt Register (INT) Addr=21h; Reset Value=00h
Bit7 Bit6 Bit5 Bit4 ICKF Bit3 ID3 Bit2 ID2 Bit1 ID1 Bit0 ID0
Persistency Check Register (PCHK-A/B) Two input signals per channel , labeled A and B, are submitted to persistency check. In dynamic mode (STA=0), A and B inputs of the four channels, are sampled on the multiplexed lines IO0 (pin13) and IO1 (pin14). In static mode (STA=1) the persistency check is performed on four pairs of lines, assigned to each channel according to the table:
CHAN# 0 1 2 3 Input A IO0 (pin 13) IO4 (pin 17) IO6 (pin 48) IO10 (pin 44) Input B IO1 (pin 14) IO5 (pin 18) IO7 (pin 47) IO11 (pin 43)
ICKF = 1: If interrupt is generated by a change of bit 0 in register ALARM. In dynamic I/O configuration the ID3..0 bits latch the interrupt request from the related channel. Any single bit IDn is cleared after reading related I/O register or by setting MCn bit High (i.e. when channel n is disabled to generate interrupt ). In static I/O configuration ID0 and ID2 bits latch the interrupt request from I/O11..0 and CS3..0 respectively: ID0 : is set High when the interrupt is requested from any the I/O11..0 lines. ID2: is set High when the interrupt is requested from any of the CS3..0 (configured as I/O). ID0 and ID2 are cleared after reading related I/O register. ID1 and ID3 are don't care. Pin strap value (value=00b):
0 0 0 0 0
Addr=1Fh; Addr=20h;
Bit7 TA7 TB7 Bit6 TA6 TB6
Reset Value=00h Reset Value=00h
Bit5 TA5 TB5 Bit4 TA4 TB4 Bit3 TA3 TB3 Bit2 TA2 TB2 Bit1 TA1 TB1 Bit0 TA0 TB0
Alarm Register (ALARM) Addr=22h; Reset Value=00h
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 POR Bit0 CKF
TA7..0 and TB7..0, content of PCHKA and PCHKB registers, define the minimum duration of input A and B to generate interrupt ; spurious transitions shorter than the programmed value are ignored. The time width can be calculated according to the formula: Time-Width A = (TA7..0) x 64s Time-Width B = (TB7..0) x 64s If PCHKA/B is programmed to 00h the persistency check is not performed and any detected transition will generate interrupt. All the inputs, with or without persistency check, are sampled with a repetition rate of 32s Pin strap value:
CKF=1: If number of PCM clock pulses in one frame period does not match expected value. POR=1: If a Power On Reset is detected during operation. The register ALARM is cleared after reading operation only if signals are inactive. Pin strap value (value=00h):
0 0
Interrupt Mask Register for Alarm (AMASK) Addr=23h; Reset Value=11b
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MCF
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STLC5046
MCF=1: The corresponding alarm bit (CKF) doesn't generate interrupt. MCF=0: The corresponding alarm bit (CKF) generates interrupt. Pin strap value (value=00h):
1 Bit7 Bit6 Bit5 R12 Bit4 R11 R31 Bit3 R10 R30 Bit2 R02 R22 Bit1 R01 R21 Bit0 R00 R20 0 0 0 0
Receive Amplifier Gain Registers (RXG-10/32) Addr: 26h; Reset Value=00h Addr: 27h; Reset Value=00h
Loopback Register (LOOPB) Addr=24h; Reset Value=00h
Bit7 DL3 Bit6 DL2 Bit5 DL1 Bit4 DL0 Bit3 AL3 Bit2 AL2 Bit1 AL1 Bit0 AL0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Rn2
R32
Rn1
Rn0 0 1 0 1 0 1 0 1
Receive Amplifier Gain Ch#n (dB) Mute -13.98 -7.96 -4.44 -1.94 0 0 0
DL3..0=0: Normal Operation DL3..0=1: Codec #3..0 is set in Digital Loopback mode, this means that the receive PCM signal applied to the programmed Receive Time Slot is transferred to the programmed Transmit Time Slot. AL3..0=0: Normal Operation AL3..0=1: Codec #3..0 is set in Analog Loopback mode, this means that the VFRO signal is tranferred to the VFXI input internally into the Codec. When loopbacks are enabled the signal appears also at the corresponding VFRO output. It is possible to have no signal on the VFRO output programming the GR register to 00h in case of digital loopback. Pin strap value (value=00h):
0 0 0 0 0 0 0 0
Overall receive gain depends on the receive amplifier gain (Rn2..0 setting in RXG reg.) and digital gain (GRXn reg. setting). As a reference : when Rn2..0 is set for 0dB gain and GRXn=FFh (max. gain) 0dBm0 at DR input correspond to a level at VFRO output equal to 547mVrms (e.g. -3dBm 600ohm) Pin strap value :
Rn2 GRn = 1 1 1 Rn1 1 0 Rn0 1 0
Transmit Preamplifier Gain Register (TXG) Addr=25h; Reset Value=X0h
Bit7 Bit6 Bit5 Bit4 Bit3 XG3 Bit2 XG2 Bit1 XG1 Bit0 XG0
GRn = 0
Overall gain including also GRXn; GRn = 1: -0.8dB; GRn = 0: -4.3dB. Silicon Revision Identification Code (SR=D) Addr: 31h; Read Only.
X X X X 0 0 0 0
XG3..0=0:Transmit preamplifier gain ch. 3..0= 0dB XG3..0=1:Transmit preamplifiergainch. 3..0= 3.52dB Overall transmit gain depends on combination of TXG and GTXn registers. For XGn=0 and GTXn=FF 0dBm0 at DX output correspond to 15dBm|600 (137mVrms) at VFXI input. Pin strap value (value=00h):
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VCC(3.3V) 0.1F VDD(3.3V) VCC VCC 61 60 59 58 RAC ZAC 20 19 25 RDC ILTF 26 RX 33 VFRO0 CRX MODE 41 39 17 43 44 3 4 5 6 7 1 2 8 30 23 42 TO OTHER SLICs RTH TTXIN CKRING CRT 11 CRT RLIM 31 RLIM REF 32 33 IREF 27 36 35 16 RT2 VREG BASE VBAT CVB CSRV 34 CREV CREV CSRV AGND and BGND must be shorted together on the LINE CARD VBAT VBAT QEXT VRING RS2 TIP RP1 TX CTX 100nF DET GDK/AL D0 D1 D2 R0 R1 CSOUT TO OTHER SLICs CS0 CSIN RES RTH 28 29 53 53 VFRO1 VFXI1 VFRO2 VFXI2 VFRO3 VFXI3 39 38 42 43 48 46 CS3 CS2 CS1 24 RP2 TIP 22 CAC CAC RT 18 14 RS RDC RS CH ZB ZB ZA CC 57 IO11 VREL IO10 21 RELR IO9 ZAC1 12 9 10 29 37 13 REL1 IO8 VDD VCC AGND BGND REL0 IO7 VCC (5V)
GND
VDD
VDD
9
VEE
0.1F
VSS
8
SUB
41
GRX=+6dB GTX=-12dB
DX
DR
11
10
FS
PCM INTERFACE
MCLK
14
13 VFXI0 35 IO0 19 IO1 IO2 IO3 IO4 IO5 IO6 20 21 22 23 24 62
TSX
12
M0
27
STLC5046
40 38 28
STLC3080
PCD RING RP1
VBAT
LCP 1511 RING RT1 RS1 RR RP2
VCC
M1
54
INT
3
CS
CCLK
4
CO
7
SERIAL CONTROL PORTS
CI
5
6
CAP
40
Figure 5. Typical Application Circuit with STLC3080 without Metering Pulse injection and I/O pins in dynamic mode.
CAP 0.1F
D99TL430
STLC5046
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STLC5046
ELECTRICAL CHARACTERISTICS (Typical value 25C and nominal supply voltage. Minimum and maximum value are guaranteed over the temperature 0 to 70C range by production testing and supply voltage range shown in the Operating Ranges. Performances over -40 to +85C are guaranteedby product characterisation unless otherwise specified.) DIGITAL INTERFACE
Symbol Vil Vih Iil Iih Ci Vol Voh Parameter Input Voltage Low DI pins Input Voltage High DI pins (1) Input Current Low DI pins Input Current High DI pins Input Capacitance (all dig. inp.) Output Voltage Low DX, TSX pins Output Voltage High DX pinn Iol = 3.2mA (other pins Iol = 1mA) 0 Ioh = -3.2mA (other pins Iol = 1mA) 0.85VDD Test Condition Min. 0 0.8V DD -10 -10 5 0.4 VDD Typ. Max. 0.2VDD 5.5 10 10 Unit V V A A pF V V
ANALOG INTERFACE
RIX ROR Transmit Input Amplifier Input Impedance (VFXI) Receive Output Impedance (-1.0V< VFRO<1.0V,IVFRO= 1mA 1000 1 M
POWER DISSIPATION
Idd (pd) Idd Power down Current Active Current 9 48 11 60 mA mA
MASTER CLOCK TIMING
fMCLK Frequency of MCLK frequency is automatically detected 1.536 1.544 2.048 4.096 8.192 40 40 15 15 MHz MHz MHz MHz MHz ns ns ns ns
tWMH tWML tRM tFM
Period of MCLK high Period of MCLK low Rise Time of MCLK Fall Time of MCLK
Measured from VIH to VIH Measured from VIL to VIL Measured from VIL to VIH Measured from VIH to VIL
PCM INTERFACE TIMING
tHMF tSFM tDMD tDMZ(2) tSDM tHMD tDZC(2) tXDP Hold Time MCLK low to FS low Setup Time, FS high to MCLK low Delay Time, MCLK high to data valid Delay Time, MCLK low to DX disabled Setup Time, DR valid to MCLK low Hold Time, MCLK low to DR invalid Delay Time, MCLK low to TSX high Delay Time, MCLK high to TSX low 10 10 10 Pull up resistor = 1k Cload = 30pF 5 15 5 Pull up resistor = 1k Cload = 30pF 40 10 40 ns ns ns ns ns ns ns ns
(1) All the digital input are five-volt tollerant - maximum DC voltage 5.5V - maximum peak voltage 6.5V (2) It is defined as the time at which the output achivies the off state.
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STLC5046
Figure 6a. Pin-strap mode Short Frame Sync. Timing.
tRM
tFM 4 5
tWMH 6 tWML 7 16 17
MCLK
1 tWFH tHMF tSFM
2
3
FS
tDMD tDMZ
DX
1
2 tSDM
3 tHMD
4
5
6
7
16
DR
1
2
3
4
5
6
7
16
TSX
tXDP
D98TL386C
tDZC
Note: TWFH has to be shorter than or equal to 3 MCLK period to select Short Frame.
Figure 6b. Pin Strap mode Long Frame Sync. Timing.
tHMF 1 2 tWFH tSFM 3
tRM 4
tFM 5
tWMH 6 tWML 7 16 17
MCLK
FS
tDMZ
DX
tDMD 1 2 tSDM 3 tHMD 4 5 6 7 16
DR
1
2
3
4
5
6
7
16
TSX
tXDP
D98TL387C
tDZC
Note: TWFH has to be longer than 3 MCLK period to select Long Frame.
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STLC5046
Figure 6c. MCU Mode Frame Sync. Timing.
tHMF
tRM 1 2 3 4
tFM 5
tWMH 6 tWML 7 16 17
MCLK
tSFM
FS
tDMZ tDMD 1 2 tSDM 3 tHMD 4 5 6 7 16
DX
DR
1
2
3
4
5
6
7
16
TSX
tXDP
D98TL388C
tDZC
ELECTRICAL CHARACTERISTICS (continued) SERIAL CONTROL PORT TIMING
Symbol fCCLK tWCH tWCL tRC tFC tHCS tSSC tSDC tHCD tDCD tDSD tDDZ(1) Parameter Frequency of CCLK Period of CCLK high Period of CCLK low Rise Time of CCLK Fall Time of CCLK Hold Time, CCLK high to CS- low Setup Time, CS- low to CCLK high Setup Time, CI valid to CCLK high Hold Time, CCLK high to CI invalid Delay Time, CCLK low to CO data valid Delay Time, CS-low to CO data valid Delay Time CS-high or 8th CCLK low to CO high impedance whichever comes first Hold Time, 8th CCLK high to CS- high Setup Time, CS- high toCCLK high Pull up resistor = 1k Cload = 30pF 10 10 Measured from VIH to VIH Measured from VIL to VIL Measured from VIL to VIH Measured from VIH to VIL 5 10 20 10 30 20 50 10 100 100 20 20 Test Condition Min. Typ. Max. 4.096 Unit MHz ns ns ns ns ns ns ns ns ns ns ns
tHSC tSCS
ns ns
(1) It is defined as the time at which the output achivies the off state.
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STLC5046
Figure 7. Serial control port timing.
tRC tFC 5 6 7 8 tSCS tHCS 1 tHCS 2 tSCS tWCH 3 4 tWCL 5 6 7 8 tHSC
CCLK
tHCS
1 tSSC
2
3
4
CS-
BYTE 1 tHCD tSDC
te tDSD tDCD
BYTE 2 tDDZ
CO
7
6
5
4
3
2
1
0
CI
7
6
5
4
3
2
1
0
D99TL454
ELECTRICAL CHARACTERISTICS (continued) SLIC CONTROL INTERFACE TIMING
Symbol TCS tcsw tDIV tDII tDOA tDON Parameter Chip Select repetition rate Chip select pulse width Time CS low to data input valid Time data input invalid to CS high Time data output available to CS low Time CS high to data output not available 1.8 1.8 Test Condition Min. Typ. 31.25 3.90 1.65 1.65 Max. Unit s s s s s s
Figure 8. SLIC Control port timing.
tDIV tDOA tDII tDON 31.25s (32KHz)
CS1
CS2
CS3
CS4
IO (OUT)
OUT CH0
OUT CH1
OUT CH2
OUT CH3
OUT CH0
OUT CH1
IO (IN)
IN CH0
IN CH1
IN CH2
IN CH3
IN CH0
IN CH1
D99TL460
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STLC5046
TRANSMISSION CHARACTERISTICS TRANSMISSION TRANSFER CHARACTERISTICS
Symbol Parameter Absolute levels (see Table 19) The nominal 0dBm0 levels are: TXG = 0dB, GTXn = 0dB (FF) GXA GXAG Transmit gain Absolute accuracy Transmit gain variation with programmed gain (within 3dB from max. dig. level) Gain variation with frequency (relative to gain at 1004Hz); 0dBm0 input signal 50Hz 60Hz 200Hz 300-3000Hz 3400Hz 4000Hz 4600Hz and above Gain variation with temperature Gain variation with Supplies 5% 0dBm0 Input Signal Gain Tracking with Tone (1004Hz Law, 820Hz ALaw) Quantization Distortion with Tone (1004Hz Law, 820Hz ALaw) Transmit Noise C Message Weighted ( Law) Transmit Noise Psophometric Weighted (A Law) Differential Envelope Delay (1 to 2.56KHz Input Sinewave @ 0dBm0) -0.15 -0.2 Test Condition Min. Typ. Max. Unit
137 0.15 +0.2
mVrms dB dB
GFX
dB -20 -20 0 0.15 0 -14.0 -32.0 0.10 0.05 0.2 0.4 1.2 dB dB dB
-1.8 -0.15 -0.7
GAXT GAXE GTX
-0.10 -0.05 GSX = 3 to -40dBm0 GSX = -40 to -50dBm0 GSX = -50 to -55dBm0 VFXI = +3dbm0 VFXI = 0 to -30dBm0 VFXI = -40dBm0 VFXI = -45dBm0 -0.2 -0.4 -1.2 33 36 30 25
QDX
dB
NCT NPT DDX(1)
12 -68 500Hz 604Hz 1000Hz 1792Hz 2604Hz 2792Hz 170 110 25 0 70 95 420 -46
dBrnCo dBm0p s
DAX(1) DPXM
DPXA
Absolute Delay @ 1KHz 500 to 2800Hz Single Frequency Distortion (Mu Law 0dBm0 Sinewave @ 1004Hz) Single Frequency Distortion (ALaw 0dBm0Sinewave @ 820Hz)
s dB
-46
dB
RECEIVE TRANSFER CHARACTERISTICS
Absolute levels The nominal 0dBm) levels are VFRO: RGX = 0dB, GRXn = 0db (FF) Transmit gain Absolute accuracy (within 3dB from max. dig. level) 547 mVrms
GRA
-0.15
0.15
dB
(1) Typical value not tested in production.
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STLC5046
TRANSMISSION CHARACTERISTICS RECEIVE TRANSFER CHARACTERISTICS (continued)
Symbol GRAG GFR Parameter Receive Gain Variation with programmed gain Gain variation with frequency (relative to gain at 1004Hz); 0dBm0 input signal. Test Condition Min. -0.2 Below 200Hz 200Hz 300-3000Hz 3400Hz 4000Hz 0dBm0 Input Signal VCC = VDD = 3.3V 5% DR = 3 to -40dBm0 DR = -40 to -50dBm0 DR = -50 to -55dBm0 DR = DR = DR = DR = 3 dBm0 0 to -30dBm0 -40dBm0 -50 to -55dBm0 Typ. Max. +0.2 0.15 0.15 0.15 0 -14 +0.1 0.05 0.2 0.4 1.2 Unit dB dB
-0.25 -0.15 -0.7 -0.1 -0.05 -0.2 -0.4 -1.2 33 36 30 25
GART GARE GTR
Gain variation with temperature Gain variation with supplies Gain Tracking with Tone (1004Hz Mu Law, 820Hz A Law) Quantization Distortion with Tone (1004Hz Mu Law, 820Hz A law) Out of band spourious Noise 0dBm0 180 to 3400Hz Sinewave at DR Receive Noise C Message Weighted ( Law) Receive Noise Psophometric Weighted (A Law) Differential Envelope Delay (1 to 2.56kHz Input Sinewave @ 0dBm0)
dB dB dB
QDR
dB
GSPR
32
dB
NCR NPR DDR (1)
8 -82 500Hz 604Hz 1000Hz 1792Hz 2604Hz 2792Hz
11 -79 25 0 0 0 90 115 440 -46
dBrnCo dBm0p s
DAR(1) DPR1 PSRR CTX-R
CTR-X
CT-ICH
Absolute Delay @ 1kHz 500 to 2800Hz Single Frequency Distortion (0dBm0 Sinewave @ 1004Hz) Power Supply Rejection Ratio 1kHz, 50mVrms Transmit to Receive Crosstalk (input signal 200Hz to 3450Hz at 0dBm0) Receive to Transmit Crosstalk (input signal 200Hz to 3450Hz at 0dBm0) Inter Channel Crosstalk, TX and TX direction.
s dB dB
30 -76
dB
-76
dB
Input 200 to 3450Hz at 0dBm0 at VFXI of one channel; all other VFXI inputs and all DR inputs receive idle signal. Output is measured at DX of the 3 idle channels. Input 200 to 3450Hz at 0dBm0 at DR of one channel; all other DR inputs and all VFXI inputs receive idle signal. Output is measured at VFRO of the 3 idle channels.
-78
dB
(1) Typical value not tested in production.
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STLC5046
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.40 0.05 1.35 0.18 0.12
mm TYP. MAX. 1.60 0.15 1.40 0.23 0.16 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00 0.75 1.45 0.28 0.20 0.002 0.053 0.007 MIN.
inch TYP. MAX. 0.063 0.006 0.055 0.009 0.057 0.011
OUTLINE AND MECHANICAL DATA
0.0047 0.0063 0.0079 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0157 0.0236 0.0295 0.0393
0(min.), 7(max.)
TQFP64
D D1 A D3 A1 48 49 33 32
0.10mm Seating Plane
A2
B
E3
E1
64 1 e 16
17 C
L1
E
L
K
TQFP64
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B
STLC5046
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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